1. Field of the Invention
The present invention relates to a logic storing circuit composed of an edge-triggered-latch capable of latching input data when it is triggered by edges of a driving clock, and a logic circuit including means for supplying the driving clock to the logic storing circuit.
2. Description of the Prior Art
In the prior art, as the edge-triggered-latch (abbreviated as an "FF" (Flip-Flop) hereinafter) of this type, two kinds of circuits have been known commonly, i.e., one is such a circuit that data can be latched when the circuit is triggered by only one of leading and trailing edges of the clock (referred to as a "single FF circuit" hereinafter) and the other is such a circuit that data can be latched when the circuit is triggered by both the leading and trailing edges of the clock (referred to as a "double FF circuit" hereinafter).
As shown in FIG. 1, the single FF circuit, which is indispensable for constituting a sequential logic circuit, is composed of a master latch portion 101 which is turned into a through state in an "L" level phase of a clock CK and a slave latch portion 102 which is turned into the through state in an "H" level phase of the clock CK, both being connected in series with each other. More particularly, the master latch portion 101 is made up of a transfer gate 103 which may transfer input data IN in the "L" level phase (Ma in FIG. 2) of the clock CK, and a latch 104 which consists of two inverters 104a, 104b. Similarly, the slave latch portion 102 is made up of a transfer gate 105 which may transfer an output of the latch 104 in the "H" level phase (Sa in FIG. 2) of the clock CK, and a latch 106 which consists of two inverters 106a, 106b.
In the single FF circuit constituted as above, as illustrated in a timing chart in FIG. 2, input data IN are latched and output data OUT are output when the single FF circuit is triggered only by such edges that the clock CK rises up from the "L" level to the "H" level, i.e., leading edges of the clock CK. The input data IN are not latched when the single FF circuit is triggered by such edges that the clock CK falls down from the "H" level to the "L" level.
FIG. 3 is a schematic circuit diagram showing a configuration of a clock tree portion for driving the single FF circuit shown in FIG. 1.
The clock tree portion consists of a PLL (Phase Locked Loop) circuit 201 for generating an LSI internal clock (oscillation frequency f) to synchronize with an external clock CLK, and a clock buffer circuit 202 for driving the internal clock output from the PLL circuit 201. An output CK of the clock buffer circuit 202 is fed back to an input side of the PLL circuit 201 as a reference clock. This feed-back is to adjust the internal clock CK output from the clock buffer circuit 202 in phase so as to achieve coincidence of respective leading edges of the external clock CLK and the internal clock CK.
At the same time when the internal clock CK which is output from the clock buffer circuit 202 is supplied to the single FF circuit 301 via a signal line 203, an inverted signal CKB of the internal clock CK is also supplied to the single FF circuit 301 via an inverter 204.
In this manner, in the single FF circuit constructed as above, because of the circuit configuration, data can be latched only when the single FF circuit is triggered by one of edges of the clock. Hence, if the single FF circuit is applied to the high speed logic circuit, a frequency of the supplied clock has to be set higher. As a result, power consumption caused by switching operations in the clock tree portion would be increased. In addition, the single FF circuit is subjected conspicuously to the influence of parasitic inductance component when the high frequency clock is transferred therethrough. Hence, in order to adjust skew between local clocks distributed in respective regions of the chip and to suppress "rounding" of waveform of the clock, there is necessity of improvements in circuit design.
In order to overcome the problems of the supplied clock in the above single FF circuit, a double FF circuit shown in FIG. 4 has already been proposed wherein data can be latched to synchronize with both the leading and trailing edges of the clock.
In this double FF circuit, circuits in which output transfer gates 405, 408 are provided respectively to output stages of the master and slave latches 401, 402 are connected in parallel between clocks CK2 whose frequency is 1/2 of clock CK. The output transfer gates 405, 408 are opened and closed in an opposite phase of the clock to input transfer gates 403, 406. In FIG. 4, a reference 401 denotes a master latch portion; 402, a slave latch portion; 403, an input transfer gate of the master latch portion 401; 404, a latch circuit of the master latch portion 401; 405, an output transfer gate of the master latch portion 401; 406, an input transfer gate of the slave latch portion 402; 407, a latch circuit of the slave latch portion 402; and 408, an output transfer gate of the slave latch portion 402.
As would be evident from a timing chart illustrated in FIG. 5, in the double FF circuit having the above configuration, input data IN can be latched and output data OUT can be output when the double FF circuit is triggered by both the leading and trailing edges of the clock CK2.
FIG. 6 is a schematic circuit diagram showing a configuration of a clock tree portion for driving the double FF circuit shown in FIG. 4.
In the clock tree portion in FIG. 6, a PLL circuit 501 having a 1/2 oscillation frequency and a clock buffer circuit 502 having a twice driving force are provided in place of the PLL circuit 201 and the clock buffer circuit 202 in the configuration shown in FIG. 3. The internal clock CK2 output from the clock buffer circuit 502 is supplied to the double FF circuit 601 via a signal line 503 and at the same time an inverted signal CK2B of the internal clock CK2 is supplied to the double FF circuit 601 via an inverter 504.
With the above configuration, even if the clock CK2 having a frequency which is half of the clock CK being supplied to the single FF circuit is employed, the double FF circuit becomes equivalent in circuit function to the single FF circuit. Not only the influence of parasitic inductance component can be lessened because of reduction by half in the clock frequency to thus improve skew between the local clocks and "rounding" of the clock waveform, but also the switching frequency per unit time in the clock tree portion can be reduced to half in contrast to the single FF circuit. Therefore, reduction in power consumption can be expected by the above double FF circuit.
In the meanwhile, the single FF circuit and the double FF circuit as described above have been constructed to hold statically the logic value between the input and output transfer gates. On the contrary, a double FF circuit composed of a so-called dynamic latch has been known in the art (see Patent Application Publication Laid-open No. 6-237152).
FIG. 7 is a circuit diagram showing another double FF circuit disclosed in the above Patent Application Publication in the prior art.
In this double FF circuit in FIG. 7, data of the master and slave latches can be held dynamically as charges accumulated respectively on nodes between clocked inverters 701, 702 and between clocked inverters 801,802. Taking account of the fact that to introduce newly the input logical value into either the master latch or the slave latch is not needed in the case that the input logical value and the output logical value are equal to each other, a new logical value can be latched by supplying a clock signal .phi. to the input side clocked inverters 701, 801 with the use of a circuit consisting of an EX-OR gate 901, an AND gate 902, and an OR gate 903 only in the case that the input logical value and the output logical value are not equal to each other.
However, in the double FF circuit shown in FIG. 4, the circuits provided on the output stages of the master and slave latches 401, 402 which are connected in parallel with each other are composed of the transfer gates 405, 408 which are controlled by the clock CK2. For this reason, gate capacitance load connected to the clock nodes becomes doubled in comparison with the single FF circuit shown in FIG. 1. Accordingly, an advantage of reducing power consumption in the clock tree portion due to reduction in the clock frequency mentioned above has been canceled.
Then, in the double FF circuit disclosed in the Patent Application Publication and shown in FIG. 7, the clock signal .phi. used to control the overall circuit is supplied via the AND gate 902 and the OR gate 903 to the upper and lower clocked inverters 701, 801 which are provided in the vicinity of the input D, nevertheless the clock signal .phi. is supplied directly to the upper and lower clocked inverters 702, 802 which are provided in the vicinity of the output Q. In other words, as in the double FF circuit shown in FIG. 4, the number of logical devices connected to the clock nodes is four and therefore, like the above, the advantage of reducing power consumption in the clock tree portion has been canceled.